Ingrid Lee, Taipei; Adam Hwang

 

Taiwan Semiconductor Manufacturing Company (TSMC) has undertaken in-house high-end packaging of ICs produced by its foundry processes for fabless IC design houses in the US and Europe mainly, posing competition with Taiwan-based providers of outsourced IC packaging/testing services, according to suppliers of semiconductor equipment.

Fabless IC design houses are willing to have TSMC responsible for front-end foundry and back-end packaging services although TSMC's packaging ASPs (average selling prices) are higher than those of IC packaging/testing service providers, the sources pointed out. This is because these fabless IC design houses like the convenience of a one-stop solution and worry about lower yield rates due to outsourced packaging, the sources indicated.

TSMC focuses on high-end packaging of ICs based on 28nm process, including FC (flip chip) CSP (chip scale package) and WLCSP (wafer level CSP), the sources indicated. Since TSMC has gross margins of 50-60% for foundry services but those of only 20-30% for packaging services, it may not be economical for TSMC to invest in packaging equipment, the sources pointed out.

So far, no Taiwan-based IC design houses have accepted TSMC's higher quotes for packaging services, the sources noted.